From a product point of view, the present invention relates to a running-average filter, also referred to hereafter as a decimation filter, which is connected to the output of an oversampling-type A/D converter circuit. From a technological point of view, on the other hand, the present invention relates to an effective technique suitable for a communication/transmission apparatus such as an echo-canceller transmission apparatus.
An oversampling-type A/D converter circuit outputs one to several-bit data as a conversion result which has a relatively low accuracy. However, an extremely high number of pieces of output data can be obtained by increasing the sampling clock frequency to a value typically as high as 5.12 MHz. In addition, by applying a running-average operation on data output by such an oversampling-type A/D converter circuit, a conversion result can be derived from the output data with a high degree of accuracy. In the running-average operation, certain weights are applied according to impulse responses and an average value or a root mean square value is computed. The running-average operation can be executed by means of a decimation filter. When the oversampling-type A/D converter and the decimation filter are employed in a system, in which the output phase of its digital data is variable, such as a communication/transmission apparatus, for example, the signal with a variable output phase is supplied to a DPLL (Digital Phase Locked Loop) circuit. An example of a signal with a variable output phase is a waveform-equalized signal output by the conventional decimation filter. The DPLL circuit synchronizes the phase of a sampling clock signal with the waveform-equalized signal having a variable output phase. In this way, the decimation filter can immediately output correct values in accordance with the phase variations. The fact that the decimation filter can immediately output correct values in accordance with the phase variations is desirable for obtaining a stable operation or good data transmission characteristics out off the entire system in which the digital data has a variable output phase.
An example of a decimation filter, which takes this desirable capability into consideration, is disclosed in the U.S. Pat. No. 4,983,975 dated Jan. 8, 1991. The decimation filter typically comprises three types of filters FIRA, FIRB and FIRC connected to the output of an oversampling-type A/D converter circuit 1 for converting an analog signal Ain into digital data as shown in FIG. 9. The circuits of the filters FIRA, FIRB and FIRC are identical with one another but each supplied with a clock signal having a frequency different from each other. The clock signals are supplied by a control circuit CTL denoted by reference numeral 7-3 so that the filters FIRA, FIRB and FIRC typically calculate leading-phase, unchanged-phase and lagging-phase outputs of the oversampling-type A/D converter circuit 1. The generation of the clock signals by the control circuit CTL is based on a sampling clock signal .phi.os. Receiving a leading-phase signal Lead and a lagging-phase signal Lag from the DPPL circuit, the control circuit CTL further provides a select circuit SET denoted by reference numeral 13 with a command signal for selecting one of signals output by the filters FIRA, FIRB and FIRC. Receiving the command signal from the control circuit CTL, the select circuit SEL forwards one of the signals output by the filters FIRA, FIRB and FIRC. A register REG denoted by reference numeral 6 latches a signal output by the select circuit SEL, outputting digital data synchronized with data-processing timing of a digital circuit at a later stage. With this decimation filter, the integration phase of the decimation filter can be controlled in .phi.os-period units, where Ous is the sampling clock signal as cited above. As a result, the decimation filter functions correctly even for a system in which the output phase of its digital data varies.
In the case of the conventional technology described above, however, three filters each having a circuit configuration identical with each other are required in the filter unit which determines the circuit size of the decimation filter. The variable-output-phase decimation filter is inevitably about three times larger than a decimation filter applied to a system in which the output phase of its digital data is fixed.